1. Field of the Invention
The present invention relates to a semiconductor integrated circuit incorporating a spread spectrum clock generator and a method for testing the semiconductor integrated circuit.
2. Description of Related Art
There is a possibility that an electromagnetic wave, generated by a clock signal propagating through a circuit in an electronic device, affects the operation, or the like, of other electronic devices as EMI (Electro-Magnetic Interference) noise. As a method for reducing the EMI noise, Japanese Laid-Open Patent Publication No 9-98152 describes a method by which a peak value is lowered by periodically fluctuating the frequency of a clock used in an electronic device and thereby spreading the frequency spectrum thereof. The greater the fluctuations in the frequency, the higher degree of effectiveness in reducing EMI noise is obtained. However, since the fluctuations in the frequency change into a kind of jitter, too great fluctuations in the frequency cause an operational problem in the circuit. As a result, it is common to set the fluctuation width (modulation width) of the frequency at about a few tenths of a percent to a few percent of the reference frequency.
A circuit for generating the above-described clock signal having a fluctuating frequency is a spread spectrum clock generator (SSCG). The SSCG is sometimes provided as a single LSI (Large-Scale Integrated Circuit) chip, and is sometimes built into a system LSI. When the SSCG is built into the system LSI, as part of the test conducted at the time of shipment of the LSI, it is necessary to test to see whether or not a clock signal generated by the built-in SSCG is appropriately modulated. To do this, it is common to extract the clock signal outputted from the SSCG to the outside of the LSI via a signal line, and check the spectrum by an analog tester. However, the problem is that the measurement made by the analog tester takes time to conduct a test. Moreover, since the clock signal is affected by noise on the signal line used for extracting the clock signal to the outside of the LSI or on the testing board, it becomes sometimes difficult to measure frequency fluctuations as small as about a few tenths of a percent to a few percent.
Furthermore, the tester used for a test of a system LSI is generally a digital tester, and a test using an analog tester is separately performed in addition to a test using the digital tester, which reduces test efficiency. However, to conduct a test on a SSCG by using the digital tester, it is necessary to operate the digital tester at a frequency which is 100 to 1000 times the reference frequency of the SSCG to measure frequency fluctuations as small as about a few tenths to a few percent. It is practically impossible to operate the digital tester at such a fast frequency.